In general, a semiconductor device formed on a semiconductor substrate made of, for example, silicon, is formed through a series of unit processes, including a film stacking process, impurity doping process, a photolithography process for patterning films, and an etching process. In order to determine whether each unit process has accurately been performed to be adapted to the design, failures of manufactured semiconductor devices, including transistors, capacitors, resistors, inductors, and so on, are detected or parameter characteristics thereof are evaluated whenever the unit process is completed.
As described above, in order to evaluate electrical properties of semiconductor devices, test elements are formed together with the semiconductor devices. The test elements are generally formed on scribe line regions existing between adjacent integrated circuit chips on a semiconductor substrate.
A test element is electrically connected to a pad. In order to test a test element, a probe terminal is brought into contact with the pad to apply a predetermined signal to the test element. Then, the signal output through the pad is analyzed to evaluate the electrical properties of semiconductor devices.
However, the respective pads, excluding those pads for grounding, are electrically connected to one test element, to then be used to test one test element. Therefore, as the number of test elements to be tested increases, the number of pads increases. However, since a space of a semiconductor device in which pads are to be formed is restricted, there exists a need for a method of more efficiently testing a test element using a restricted number of pads.